1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor.
2. Description of Related Art
Very large scale integration (VLSI) circuits having a narrower line width is now packaged inside an ever-increasing silicon wafer. Such trend enables the inclusion of more functions into an identical piece of silicon chip resulting in a drop in price. To increase market competition, semiconductor manufacturer routinely integrates read-only-memory (ROM), static random access memory (SRAM), flash memory or dynamic random access memory (DRAM) with logic circuits and digital circuit together on the same piece of silicon chip. Such integrated produces a light, thin and compact chip often referred to as a system on chip (SOC).
Forthcoming generation of system chips all attempts to produce breakthrough in dimensional reduction and reliability improvement. To produce a system chip having a smaller dimension and higher reliability and to provide sufficient metallic interconnects within limited chip area for linking up devices, borderless contact technique is necessarily employed.
To shrink device dimension, conventional method of manufacturing the P-channel metal-oxide-semiconductor (PMOS) of a DRAM within the system chip includes forming gate electrode and gate spacers on a substrate. Thereafter, ions are implanted into the substrate to form source/drain regions. The method of producing a borderless contact includes forming a silicon nitride layer over the substrate and conducting a borderless contact etching using the silicon nitride layer as an etching stop.
However, the aforementioned method of using the silicon nitride layer to serve as an etching stop may lead to threshold voltage (Vt) stability problem. This is because silicon nitride contains some hydrogen atoms that may diffuse during a thermal treatment. Ultimately, the presence of atomic hydrogen inside the silicon nitride layer affects the performance of the MOS transistor. The situation is made worse after a reduction in device dimension. To lower junction leakage, a low thermal budget method such as plasma-enhanced chemical vapor deposition (PECVD) is used to form the silicon nitride layer. During plasma deposition of silicon nitride, hydrogen atoms within the plasma reacts with unsaturated/unbonded silicon atoms and nitrogen atoms to form Sixe2x80x94H and Nxe2x80x94H bonds. Consequently, concentration of hydrogen atoms within the silicon nitride layer is extremely high leading to serious threshold voltage instability after thermal diffusion.
Accordingly, one object of the present invention is to provide a method of manufacturing a metal-oxide-semiconductor (MOS) transistor capable of reducing concentration of hydrogen within a silicon nitride etching stop layer.
A second object of this invention is to provide a method of manufacturing a MOS transistor capable of improving threshold voltage stability.
A third object of this invention is to provide a method of manufacturing a MOS transistor capable of improving reliability of the MOS transistor.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the gate electrode and the source/drain regions. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5xc3x971013xcx9c5xc3x971014 cm xe2x88x922 and at an implantation energy level between 2 KeVxcx9c5 KeV.
The embodiment of this invention can be applied to the fabrication of a static random access memory (SRAM). First, a substrate having a gate structure thereon is provided. The gate structure includes a gate oxide layer, a gate electrode, gate spacers on sidewalls of the gate electrode and a pair of source/drain regions. A self-aligned silicide layer is formed over the gate electrode and the source/drain regions using a self-aligned silicide process. A silicon nitride layer that serves as an etching top layer is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out. The fluoride blanket implantation is conducted using an implantation dosage of about 5xc3x9710135xc3x971014 cmxe2x88x922 and at an implantation energy level between 2 KeVxcx9c5 KeV. A dielectric layer is formed over the substrate. The dielectric layer is patterned to form a borderless contact opening that exposes a portion of the silicon nitride etching stop layer. The exposed silicon nitride etching stop layer is removed. A metallic layer is formed over the substrate completely filling the borderless contact opening. A chemical-mechanical polishing operation is conducted to remove excess metallic material over the borderless contact opening. Finally, conventional steps necessary for forming the remaining parts of the SRAM is carried out.
In this invention, a low-energy fluoride blanket implantation is conducted after the formation of the silicon nitride etching stop layer. The fluoride atoms capture most of the hydrogen inside the silicon nitride layer so that threshold voltage is stabilized and reliability of the transistor device is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.